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Atom: Low-bit Quantization for Efficient and Accurate LLM Serving

Paper · 2023 · Yilong Zhao, Chien-Yu Lin, Kan Zhu et al.

Summary

LLM serving relies on batching to keep GPUs busy, and quantization can further reduce memory use and compute cost. Current methods fall short. Weight-only schemes still multiply in FP16. INT8 weight-activation schemes leave INT4 Tensor Cores unused. Earlier 4-bit attempts such as OmniQuant and QLLM lose noticeable perplexity. Atom targets 4-bit quantization of both weights and activations (W4A4) without that loss.

It keeps a small set of outlier channels at higher precision (8-bit), after reordering channels so memory access stays regular. It also uses fine-grained group quantization, computes activation scales dynamically for each input, and stores the KV-cache in low bit-width. Quantization and reordering are fused into existing operators. Custom CUDA kernels for low-bit Tensor Cores are integrated, together with FlashInfer attention, into an end-to-end serving framework.

On Llama models from 7B to 65B, Atom stays close to FP16 quality. At the same latency target, it raises serving throughput by up to 7.73× over FP16 and 2.53× over INT8. This shows that accurate 4-bit serving is practical.

Key points

  • On Llama-65B with 4-bit weights and activations, the average zero-shot accuracy drop is about 1.4%, and WikiText2 perplexity rises by only about 0.3.
  • At similar latency, end-to-end throughput improves by up to 7.7× vs FP16, 5.5× vs W4A16 (weight-only), and 2.5× vs W8A8.
  • The motivation is hardware peak throughput on A100: INT4 reaches 1248 TOPS, INT8 reaches 624 TOPS, and FP16 Tensor Cores reach only 312 TFLOPS.
  • A runtime profile of Llama-7b shows that dense layers plus self-attention take over 90% of execution time. These are therefore the parts worth quantizing.
  • Symmetric quantization is used to avoid the extra cross-term computations that asymmetric zero points would add to integer matrix multiplication.

Interesting ideas

  • I1. Reorder channels before mixed precision: Outlier channels are moved to the end of the matrix so the high-precision part forms one contiguous block. This keeps mixed-precision kernels regular and fast, a trick that applies to any format mixing two precisions.
  • I2. Fuse cheap preprocessing into neighbouring kernels: Dynamic quantization and reordering are folded into operators that already run, which hides their cost. This is a general way to make per-input adaptive steps affordable.
  • I3. Use a middle tier for outliers: Outliers are stored in INT8 rather than FP16, trading a little accuracy for much better efficiency. A graded precision scheme like this may beat a strict "low vs full" split elsewhere too.
  • I4. Profile before optimizing: The paper first breaks down where serving time goes across batch sizes, then targets those layers. This is a useful evaluation habit for any efficiency project.
  • I5. Measure throughput under a fixed latency target: Results are reported at matched latency rather than as raw speed alone. This gives a fairer, deployment-relevant comparison between methods.

Our summary of the paper, in our own words — not its text. The work belongs to its authors; read it at the links above.

 Institutions

Also on the byline: Seattle University.

 Fields, topics and concepts

Cite

Cite as Yilong Zhao, Chien-Yu Lin, Kan Zhu, Zihao Ye, Lequn Chen, Size Zheng, Luis Ceze, Arvind Krishnamurthy, Tianqi Chen and Baris Kasikci. 2023. Atom: Low-bit Quantization for Efficient and Accurate LLM Serving. MLSys 2024.

The paper itself, not this page. BibTeX from the library's record of the work. arXiv 2310.19102

@inproceedings{zhao2023atom,
  title = {{Atom: Low-bit Quantization for Efficient and Accurate LLM Serving}},
  author = {Yilong Zhao, Chien-Yu Lin, Kan Zhu, Zihao Ye, Lequn Chen, Size Zheng, Luis Ceze, Arvind Krishnamurthy, Tianqi Chen and Baris Kasikci},
  booktitle = {MLSys 2024},
  year = {2023},
  eprint = {2310.19102},
  archivePrefix = {arXiv},
  url = {https://arxiv.org/abs/2310.19102}
}

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