SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization
Paper · 2026 · Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi et al.
Summary
Writing and explaining hardware code at the Register-Transfer Level (RTL) is hard for LLMs. HDL syntax is strict, annotated data is scarce, and Verilog/VHDL map poorly onto natural language. Prompting and RAG approaches also lack an explicit symbolic plan. The IBM Research authors propose SYMDIREC, a three-stage neuro-symbolic pipeline that handles both RTL synthesis (NL spec to code) and RTL summarization (code to NL):
- Divide: an LLM splits the input into sub-components, each paired with a symbolic logic form (Boolean, temporal or dataflow). For summarization, the split follows the code's AST.
- Retrieve: a retriever fine-tuned on the curated RTL-IR dataset uses those symbolic forms to fetch matching code fragments.
- Conquer: an LLM checks the candidates against the symbolic intent and assembles the final module or summary.
Only the retriever is trained; the LLM itself is not fine-tuned. Across Verilog and VHDL benchmarks, the method improves Pass@1 by about 20% and ROUGE-L by 15–20% over prompting and RAG baselines. This suggests symbolic scaffolding is a lightweight way to make hardware code generation more precise.
Key points
- The authors describe SYMDIREC as the first system to tackle synthesis and summarization jointly across both Verilog and VHDL.
- The retriever is trained on RTL-IR, a dataset drawn from GitHub projects released under reuse-friendly licenses (MIT, BSD, Apache-2.0). Public benchmarks such as Verilog-Eval are also used.
- Hyperparameter study:
- Performance rises as the number of sub-components N grows to 6, then falls.
- Retrieval depth helps up to k = 5, after which it plateaus or drops.
- The recommended default is N = 4, k = 5.
- Error analysis:
- About 8–10% of sub-components get flawed symbolic expressions.
- About 12–15% of retrieved candidates match only partially.
- About 6–8% of sub-components suffer assembly failures.
- Together these leave a ~10–15% Pass@1 gap to the oracle variant SYMDIREC-GT.
- Main limitation: only single-file RTL designs are supported, not hierarchical or multi-file projects. Weaker LLMs also produce less useful symbolic decompositions.
Institutions
Fields, topics and concepts
📚 Shelves 7The field of science this work belongs to (OpenAlex fields).Computer Science · 18,614 worksArtificial Intelligence · 17,965 worksArts and Humanities · 17,450 worksLanguage and Linguistics · 17,296 worksHardware and Architecture · 167 worksEngineering · 188 worksElectrical and Electronic Engineering · 33 works
🧭 Topics 1Research subjects and languages the work is about.Summarization · 243 works
Cite
Cite as Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi, Charles Mackin, Ashutosh Jadhav, David Beymer, Ehsan Degan and Vandana Mukherjee. 2026. SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization. Proceedings of the 19th Conference of the European Chapter of the Association for Computational Linguistics (Volume 5: Industry Track).
@inproceedings{vijayaraghavan2026symdirec,
title = {{SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization}},
author = {Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi, Charles Mackin, Ashutosh Jadhav, David Beymer, Ehsan Degan and Vandana Mukherjee},
booktitle = {Proceedings of the 19th Conference of the European Chapter of the Association for Computational Linguistics (Volume 5: Industry Track)},
year = {2026},
doi = {10.18653/v1/2026.eacl-industry.66},
url = {https://doi.org/10.18653/v1/2026.eacl-industry.66}
}References
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